The present invention relates to a system for transmitting and/or storing information through a medium of high error rate such as radio transmission path, and more specifically to a coding and/or decoding apparatus for coding a bitstream obtained by a high efficiency compression coding to an error correction and/or detection code and for transmitting and/or storing the coded bitstream.
In a system for transmitting audio and/or video signals via radio transmission path after the signals have been compression-coded at a high efficiency to reduce the signal quantity as small as possible, for instance as with the case of radio TV telephone, portable information terminal, digital TV broadcasting system, etc., since the error rate of the transmission path is relatively high, it is important to transmit the obtained bitstream in as high a quality as possible.
When the bitstream is transmitted and/or stored via a medium of high error rate as described above, an error correction code such as BCH code, RS code, convolution code, etc. has been so far widely adopted as means for reducing the error rate. On the other hand, as means for detecting an error on the reception side, an error detecting code such as check sum, CRC, etc. are used. In these error correction and/or error detection methods,. error is corrected and/or detected by adding excessive (redundant) bits to information to be transmitted and/or stored in accordance with a prescribed rule and further by checking whether the transmitted and/or stored bitstream abides by the same rule when decoded.
However, in the above-mentioned method such that the bitstream obtained by high efficiency compression coding is further coded to an error correction and/or detection code and then transmitted and/or stored, there exists a problem in that it is difficult to combine this method with a resynchronization method for recovering a synchronization when synchoronization-loss occured due to an erroneous bistream word caused by the transmission and/or storage medium. Here, as the above-mentioned synchronization restoring method, there has been widely used such a method of inserting a unique word (referred to as synchronization code or start-code) decodable uniquely (unconditionally) and of resuming decoding operation, in case of synchronization-loss, from a time point when the synchronization code is detected again.
In order to form the synchronization code as a code word decodable unequivocally, it is necessary to construct the code word in combination with another code word in such a way that a bit pattern the same as that of the synchronization code will not appear. In the case of the general error correction and/or detection coding method, however, it is difficult to construct the code word in such a way that a specific bit pattern will not appear. On the other hand, when the bit pattern the same as the synchronization code appear, pseudo-synchronizetion may occur due to an erroneous detection of the synchronization code.
To overcome this problem, conventionally, the following method has been so far used: after the error correction and/or detection coding has been executed, the presence of the bit pattern the same as that of the synchronization code is checked in the bitstream; when the same bit pattern exists, stuffing bits are inserted into the pattern in accordance with a prescribed rule; and the inserted stuffing bits are removed in accordance with the same prescribed rule by the decoding apparatus in order to prevent the pseudo-synchronization. In this method, however, when the bitstream having an error is transmitted and/or stored, since there exists a possibility that the stuffing bits are also inserted erroneously, there still exists another problem in that an additional synchronization-loss or pseudo-synchronization may occur.
Further, when the bitstream is coded for error correction and/or detection and further the synchronization code is inserted, in the conventional method, since many insertion bits must be added to the bitstream at the last portion of a synchronization block sandwiched between two synchronization codes in order to compensate for a remainder of the information bits to be coded for error correction and/or detection, there arises another problem in that the coding efficiency is lowered.
On the other hand, in order to increase the error correction and/or detection capability, although it may be considered to increase the redundancy of the information to be transmitted and/or stored, in this case, however, the number of necessary bits increases when the same quantity of the information is transmitted. Therefore, when the error correction and/or detection capability is simply increased, there arises another problem in that a transmission path of higher transmission rate is required or that the number of bits of information to be stored is increased. Further, when the transmission rate or the storage capacity is the same, the quantity of information to be transmitted and/or stored decreases with increasing redundancy. As a result; in the case where audio and video information are compression-coded at a high efficiency and then transmitted and/or stored, if the redundancy is simply increased to increase the error resistance, as-far as the transmission and/or storage rate is the same, since the information must be compression-coded down to a lesser information quantity, there causes another problem in that the audio quality and picture quality both deteriorate.
To overcome the above-mentioned problems, as the method of obtaining a high error resistance in spite of a lesser redundancy, there exists a method referred to as hierarchical coding. In this method, the audio or picture information compression-coded at a high efficiency is classified according to the degree of error which deteriorates the audio quality or the picture quality; the error correction and/or detection code of a high redundancy and thereby a high error correction and/or detection capability is adopted for the information with more importance and a large error influence; and the error correction and/or detection coding of a low redundancy and thereby a low error correction and/or detection capability is adopted for the information with less importance and a small error influence. In this method, it is possible to increase the error resistance in spite of a relatively small averaged redundancy, as compared with when a correction and/or detection code is used uniformly for all the information in the same redundancy.
For instance, in the case of the coding method such that motion compensation prediction and the orthogonal transform are combined with each other (which is widely adopted for compression-coding moving picture information at high efficiency); that is, in the case of the coding method such that the motion compensation prediction is executed for the inputted moving picture video signals, and the predicted residual is orthogonal-transformed (e.g., discrete cosine transform (DCT)), the error correction and/or detection code of strong error correction and/or detection capability is used for the motion vector information or low-order coefficients of the orthogonal transform coefficients of the prediction residual signals (because these information deteriorates picture quality largely in case an error occurs); and the error correction and/or detection code of weak error correction and/or detection capability Is used for high-order coefficients of the orthogonal transform coefficients of the prediction residual signals (because these information exerts a relatively small influence upon the picture quality).
To realize the above-mentioned hierarchical coding, it is necessary to switch the error correction and/or detection codes of different error correction and/or detection capabilities midway in the outputted bitstream. As the method of switching the error correction and/or detection codings of different error correction and/or detection capabilities, there exists such a method that header information indicative of the sort of the error correction and/or detection code is added to the bitstream. FIG. 1 shows an example of a bitstream in which the error correction and/or detection codes are switched by adding header information. In more detail, in this example, two sorts of the error correction and/or detection codes FETC1 and FEC2 are switched. In each of the headers 1101 to 1104, header information indicative of the sort of the error correction and/or detection code and a number of code word is inserted. Therefore, the coding apparatus arranges the code word coded for error correction and/or detection after each header information, and the decoding apparatus decodes the header information; and the decoding apparatus decodes the header information and after that the error correction and/or detection code in accordance with the decoded header information.
However, in the above-mentioned method of switching the error correction and/or detection codes by adding the header information, however, there arises a problem in that the number of bits of the bitstream to be transmitted and/or stored increases due to the addition of the header information. In the case where audio or video signals are compression-coded, since some bits are used for the header information, the number of bits used for the compression coding audio or video signals is inevitably reduced, with the result that the audio quality end/or the picture quality inevitably deteriorates.
As described above, when the error correction and/or detection coding is executed for a bitstream obtained by compression-coding moving picture signals, since any bit pattern is generated, in the case where the error correction and/or detection coding is combined with the synchronization method using the unique word as synchronization code, there exists a pseudo-synchronization due to erroneous detection of the synchronization code. Further, when the stuffing bits are inserted to prevent the pseudo-synchronization, there arises another problem in that the synchronization-loss and the pseudo-synchronization occur due to erroneous insertion of the stuffing bits.
Further, when the bitstream is coded for error correction and/or detection and further the synchronization code is inserted, in the conventional method, since a relatively large number of bits must be inserted to compensate for the remainder of the information bits to be coded for error correction and/or detection at the last portion of the synchronization block, there arises a problem in that the coding efficiency deteriorates.
Further, in the case of the coding and/or decoding apparatus in which the error correction and/or detection codes of different error correction and/or detection capabilities are switched by adding header information, since the number of bits to be transmitted and/or stored increases due to the addition of the header information, when audio or video signals are compression-coded at a high. efficiency and then transmitted and/or stored, the information quantity used for audio or video information inevitably decreases, with the result there exists a problem in that the audio quality and the video quality both deteriorate.
With these problems in mind, therefore, it is the first object of the present invention to provide a coding and/or decoding apparatus, which can solve such a problem as pseudo-synchronization or synchronization-loss due to erroneous detection of the synchronization code, when combined with the resynchronization method which uses both the error correction and/or detection code and the synchronization code.
Further, the second object of the present invention is to provide a coding-and/or decoding apparatus, which can increase the coding efficiency by reducing the number of bits inserted at the last portion of the synchronization block, when combined with the resynchronization method which uses both the error correction and/or detection code and the synchronization code
Further, the third object of the present invention is to provide a coding and/or decoding apparatus, which can improve the information quality by reducing the number of bits of the bitstream to be transmitted and/or stored, without adding header information indicative of the sort of the error correction and/or detection code, in the case when bitstream obtained by compression-coding audio and video signals are coded by switching a plurality of sorts of error correction and/or detection codes and then transmitted and/or stored.
To achieve the above-mentioned object, the first aspect of the coding apparatus according to the present invention provides a coding apparatus, comprising: coding means for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and bitstream assembling means for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits a any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream.
Further, the first aspect of the present invention provides a decoding apparatus, comprising: synchronization code detecting means for detecting a synchronization code from a bitstream coded to an error correction and/or detection code composed of information bits and check bits, at each of a plurality of previously determined synchronization code insertion positions thereof; bitstream disassembling means for disassembling the bitstream to extract the information bits of the error correction and/or detection code and the check bits of the error correction and/or detection code arranged at positions other than the synchronization code insertion positions; and decoding means for decoding the error correction and/or detection code on the basis of the information bits and the check bits extracted by said code disassembling means.
In the first aspect of the present invention, since the synchronization code is arranged at each of a plurality of predetermined synchronization code insertion positions in the output bitstream and further since the check bits of the error correction and/or detection code are arranged at positions other than the synchronization code insertion positions, even if the bit pattern the same as that of the synchronization code is included in the check bits, there exists no possibility that the synchronization code is detected erroneously. Therefore, it is unnecessary to use a specific error correction and/or detection code to prevent a specific bit pattern form being formed or to insert bits to protect the synchronization pattern after having been coded to the error correction and/or detection code. As a result, it is possible to increase not only the degree of freedom of selection of the usable error correction and/or detection codes but also to improve the resistance against error, because there exists no possibility that the new erroneous synchronization detection occurs due to mixture of the erroneous insertion bit.
Further, the second aspect of the present invention provides a coding apparatus, comprising: bitstream converting means for converting an inputted bitstream other than a synchronization code arranged at each of a plurality of synchronization code insertion positions previously determined in an outputted bitstream, in such a way that a Hamming distance from the synchronization code exceeds a predetermined value; coding means for coding the bitstream converted by said bitstream converting means to an error correction and/or detection code composed of information bits and check bits; and bitstream assembling means for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of the synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream.
Further, the second aspect of the present invention provides a decoding apparatus, comprising: synchronization code detecting means for detecting a synchronization code at each of previously determined synchronization code insertion positions, from a bitstream coded to an error correction and/or detection code composed of information bits and check bits and further including the inserted synchronization codes; bitstream disassembling means for disassembling the bitstream, to extract the information bits of the error correction and/or detection code and the check bits of the error correction and/or detection code arranged at positions other than the synchronization code insertion positions; decoding means for decoding the error correction and/or detection code on the basis of the information bits and the check bits extracted by said code disassembling means; and bitstream converting means for converting the bitstream other than the synchronization code arranged at each of the synchronization code insertion positions, which is decoded by said decoding means and further converted in such a way that a Hamming distance from the synchronization code in the bitstream exceeds a predetermined value, to the original bitstream.
In the second aspect of the present invention, since the bit train arranged at the synchronization code insertion position is converted in such a way that the Hamming distance from the synchronization code exceeds a predetermined value and further since the bit train is reversely converted by the decoding processing, the bit pattern the same as-that of the synchronization code will not be included in the bit train, so that it is possible to prevent the erroneous detection of the synchronization code. Further, when the bit train is converted in such a way that the Hamming distance between the synchronization code and the bitstream other than the synchronization code exceeds a predetermined value, even if an error is mixed with the bitstream, since the synchronization code can be discriminated from the bitstream other than the synchronization code, it is possible to reduce the possibility that the synchronization code is detected erroneously.
Further, since the above-mentioned conversion and/or reverse conversion processing is executed at the synchronization code insertion positions, it is possible to reduce the overhead, as compared with the prior art method such that the conversion and/or reverse conversion processing is executed all over the bitstream. In addition, in the case of the bitstream inputted to the coding apparatus, it is unnecessary to execute the conversion processing or to use a special code word, so that the bit pattern the same as that of the synchronization code can be prevented from being formed. In particular, in the case where a variable code length coding apparatus in which different code word tables are switched in use is connected to the input side of the coding apparatus according to the present invention, when the code word table is formed in such a way that the bit pattern the same as that of the synchronization code will not be formed by the variable length coding apparatus, there exists a problem in that the coding efficiency is inevitably reduced. In the present invention, however, since the coding apparatus and/or decoding apparatus as described above is used, it is possible to eliminate this problem.
Further, the third aspect of the present invention provides a coding apparatus, comprising: coding means for coding an inputted bitstream to an error correction and/or detection code; synchronization code inserting means for inserting synchronization codes into the inputted bitstream; deciding means for deciding the number of information bits to be coded to the error correction and/or detection code and arranged immediately before the synchronization code of the bitstream; and said coding means forming the error correction and/or detection code arranged immediately before the synchronization code as a degenerative code adaptively degenerated on the basis of the number of bits decided by said deciding means.
Further, the third aspect of the present invention is provides a decoding apparatus, comprising: decoding means for decoding a bitstream coded to an error correction and/or detection code and further including inserted synchronization codes; synchronization code detecting means for detecting the synchronization codes arranged in the bitstream; deciding means for deciding the number of information bits coded to the error correction and/or detection code and arranged immediately before the synchronization code detected by said synchronization code detecting means; and said decoding means decoding the bitstream by deciding whether the error correction and/or detection code arranged immediately before the synchronization code is a degenerative code or not on the basis of the number of the information bits decided by said deciding means.
In the third aspect of the present invention, since a degenerative code (whose number of bits is degenerated to a small number of bits required to code the information bits remaining at the last portion of the one synchronization period (block) is used for the error correction and/or detection code arranged immediately before the synchronization code, it is unnecessary to use many insertion bits to fill the remainder of the information bits at the last portion of the synchronization block, with the result that the coding efficiency can be increased.
Further, the fourth aspect of the present invention provides a coding apparatus, comprising: coding means for coding an inputted bitstream including a plurality of sorts of information to different error correction and/or detection codes; and switching means for switching the sorts of the error correction and/or detection codes according to the sort of the information included in the bitstream.
Further, the fourth aspect of the present invention provides a decoding apparatus, comprising: decoding means for decoding a bitstream coded to error correction and/or detection codes of different sorts according to information sort, to form original information; and means for deciding the sort of the error correction and/or detection code on the basis of the information sort formed by said decoding means, the decided sort being transmitted to said decoding means.
In the fourth aspect of the present invention, when the coding and/or decoding is executed by switching the error correction and/or detection codes according to the sort thereof, since the error correction and/or detection code is switched on the coding apparatus side according to the sort of information of the bitstream inputted to the coding apparatus, and since the error correction and/or detection code is switched on the decoding apparatus side by deciding the sort of the error correction and/or detection code on the basis of the decoded information (i.e., the same code as that used on the coding side), any header information indicative of the sort of the error correction and/or detection code is not required (being different from the prior art method), so that it is possible to eliminate the overhead due to the header information.